We have investigated post-metallization annealing (PMA) utilizing TiN gate electrode on the thin ferroelectric undoped HfO2 directly deposited on p-Si(100) by RF magnetron sputtering. By post-deposition annealing (PDA) process at 600°C/30 s in N2, the memory window (MW) in the C-V characteristics was observed in the Al/HfO2/p-Si(100) diodes with 15 to 24-nm-thick HfO2. However, it was not obtained when the thickness of HfO2 was 10 nm. On the other hand, the MW was observed for Pt/TiN/HfO2 (10 nm)/p-Si(100) diodes utilizing PMA process at 600°C/30 s. The MW was 0.5 V when the bias voltage was applied from -3 to 3 V.

In this paper, the effect of a nitrogen-doped (N-doped) LaB6 interfacial layer (IL) on p-type pentacene-based OFET was investigated. The pentacene-based OFET with top-contact/back-gate geometry was fabricated. A 2-nm-thick N-doped LaB6 interfacial layer deposited on an 8-nm-thick SiO2 gate insulator. A 10-nm-thick pentacene film was deposited by thermal evaporation at 100°C followed by Au contact and Al back gate electrodes formation. The fabricated OFET showed normally- off characteristics and a steep subthreshold swing (SS) of 84 mV/dec. from ID-VG and ID-VD characteristics. Furthermore, the aging characteristics of 6 months after the fabrication were investigated and it was found that VTH and SS were stable when the N-doped LaB6 IL was introduced at the interface between SiO2 gate insulator and pentacene.

To improve metal oxide semiconductor field effect transistors (MOSFET) performance, flat interface between gate insulator and silicon (Si) should be realized. In this paper, the influence of Si surface roughness on electrical characteristics of MOSFET with hafnium oxynitride (HfON) gate insulator formed by electron cyclotron resonance (ECR) plasma sputtering was investigated for the first time. The surface roughness of Si substrate was reduced by Ar/4.9%H2 annealing utilizing conventional rapid thermal annealing (RTA) system. The obtained root-mean-square (RMS) roughness was 0.07nm (without annealed: 0.18nm). The HfON was formed by 2nm-thick HfN deposition followed by the Ar/O2 plasma oxidation. The electrical properties of HfON gate insulator were improved by reducing Si surface roughness. It was found that the current drivability of fabricated nMOSFETs was remarkably increased by reducing Si surface roughness. Furthermore, the reduction of Si surface roughness also leads to decrease of the 1/f noise.

The AuGe-alloy source and drain (S/D) formed on SiO2/Si(100) by the lithography process was investigated for the scaling of the organic field-effect transistors (OFETs) with bottom-contact geometry. The S/D was fabricated by the lift-off process utilizing the resist of OFPR. The OFETs with minimum channel length of 2.4 µm was successfully fabricated by the lift-off process. The fabrication yield of Au S/D was 57%, while it was increased to 93% and 100% in case of the Au-1%Ge and Au-7.4%Ge S/D, respectively. Although the mobility of the OFETs with Au-7.4%Ge S/D was decreased to 1.1×10-3 cm2/(Vs), it was able to be increased to 5.5×10-2 cm2/(Vs) by the surface cleaning utilizing H2SO4/H2O2 mixture solution (SPM) and post metallization annealing (PMA) after lift-off process, which was higher than that of OFET with Au S/D.

In this research, we investigated the digital/analog-operation utilizing ferroelectric nondoped HfO2 (FeND-HfO2) as a blocking layer (BL) in the Hf-based metal/oxide/nitride/oxide/Si (MONOS) nonvolatile memory (NVM), so called FeNOS NVM. The Al/HfN0.5/HfN1.1/HfO2/p-Si(100) FeNOS diodes realized small equivalent oxide thickness (EOT) of 4.5 nm with the density of interface states (Dit) of 5.3 × 1010 eV-1cm-2 which were suitable for high-speed and low-voltage operation. The flat-band voltage (VFB) was well controlled as 80-100 mV with the input pulses of ±3 V/100 ms controlled by the partial polarization of FeND-HfO2 BL at each 2-bit state operated by the charge injection with the input pulses of +8 V/1-100 ms.

Electron cyclotron resonance (ECR) plasma oxidation of AlN thin films was studied to form the AlON high-κ gate insulator. The leakage current was found to be decreased, and also the surface roughness was improved with the ECR plasma oxidation of AlN thin films. The leakage current was further decreased after 1000 RTA in N2 with little increase of equivalent oxide thickness (EOT) because of the high quality interfacial layer formation.

In order to realize stable n-type characteristics of pentacene for applying to the organic complementary metal-oxide-semiconductor field-effect transistors (CMOS), we have fabricated pentacene based MOS diodes using ultra-thin Yb layer such as 0.5-3 nm between gate insulator and pentacene. From the results of capacitance-voltage (C-V) measurements, excellent n-type C-V characteristics of the devices with 1 and 2 nm-thick Yb were observed even though the devices were measured in air. These results suggested that the n-type semiconductor characteristics of pentacene are able to be improved by the thin Yb interfacial layer. Furthermore, the improved n-type characteristics of pentacene will enable the fabrication of flexible complementary logic circuits utilizing one kind organic semiconductor.

In this study, the effect of atomically flat Si(100) surface on Hf-based Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structure was investigated. After the atomically flat Si(100) surface formation by annealing at 1050/60min in Ar/4%H2 ambient, HfO2(O)/HfN1.0(N)/HfO2(O) structure with thickness of 10/3/2nm, respectively, was in-situ deposited by electron cyclotron resonance (ECR) plasma sputtering. The memory window (MW) of Al/HfO2/HfN1.0/HfO2/p-Si(100) diodes was increased from 1.0V to 2.5V by flattening of Si(100) surface. The program and erase (P/E) voltage/time were set as 10V/5s and -8V/5s, respectively. Furthermore, it was found that the gate current density after the 103P/E cycles was decreased one order of magnitude by flattening of Si(100) surface in Ar/4.0%H2 ambient.

In this paper, we have investigated the etching selectivity of HfN encapsulating layer for high quality PtHf-alloy silicide (PtHfSi) formation with low contact resistivity on Si(100). The HfN(10 nm)/PtHf(20 nm)/p-Si(100) stacked layer was in-situ deposited by RF-magnetron sputtering at room temperature. Then, silicidation was carried out at 500°C/20 min in N2/4.9%H2 ambient. Next, the HfN encapsulating layer was etched for 1-10 min by buffered-HF (BHF) followed by the unreacted PtHf metal etching. We have found that the etching duration of the 10-nm-thick HfN encapsulating layer should be shorter than 6 min to maintain the PtHfSi crystallinity. This is probably because the PtHf-alloy silicide was gradually etched by BHF especially for the Hf atoms after the HfN was completely removed. The optimized etching process realized the ultra-low contact resistivity of PtHfSi to p+/n-Si(100) and n+/p-Si(100) such as 9.4×10-9Ωcm2 and 4.8×10-9Ωcm2, respectively, utilizing the dopant segregation process. The control of etching duration of HfN encapsulating layer is important to realize the high quality PtHfSi formation with low contact resistivity.

In this study, the effect of nitrogen-doped (N-doped) LaB6 bottom-contact electrodes and interfacial layer (IL) on n-type pentacene-based organic field-effect transistor (OFET) was investigated. The scaled OFET was fabricated by using photolithography for bottom-contact electrodes. A 20-nm-thick N-doped LaB6 bottom-contact electrodes were formed on SiO2/n+-Si(100) substrate by RF sputtering followed by the surface treatment with sulfuric acid and hydrogen peroxide mixture (SPM) followed by diluted hydrofluoric acid (DHF; 1% HF) at room temperature (RT). Then, a 1.2-nm-thick N-doped LaB6 IL was deposited at RT. Finally, a 10-nm-thick pentacene film was deposited at 100°C followed by the Al back-gate electrode formation by using thermal evaporation. The current of electron injection was observed in the air due to the effect of surface treatment and N-doped LaB6 IL.

In this paper, we have investigated the PdEr-silicide formation utilizing a developed PdEr-alloy target for sputtering, and evaluated the contact resistivity of PdEr-silicide layer formed on n-Si(100) by dopant segregation process for the first time. Pd2Si and ErSi2 have same hexagonal structure, while the Schottky barrier height for electron (Φbn) is different as 0.75 eV and 0.28 eV, respectively. A 20 nm-thick PdEr-alloy layer was deposited on the n-Si(100) substrates utilizing a developed PdEr-alloy target by the RF magnetron sputtering at room temperature. Then, 10 nm-thick TiN encapsulating layer was in-situ deposited at room temperature. Next, silicidation was carried out by the RTA at 500 for 5 min in N2/4.9%H2 followed by the selective etching. From the J-V characteristics of fabricated Schottky diode, qΦbn was reduced from 0.75 eV of Pd2Si to 0.43 eV of PdEr-silicide. Furthermore, 4.0x10-8Ωcm2 was extracted for the PdEr-silicide to n-Si(100) by the dopant segregation process.

In this paper, we have investigated the characteristics of PdYb-silicide layer formed by the silicidation of Pd/Yb/n-Si(100) stacked structures for the first time. Pd (12-20 nm)/Yb (0-8 nm) stacked layers were deposited on n-Si(100) substrates by the RF magnetron sputtering at room temperature. Then, 10 nm-thick HfN encapsulating layer was deposited at room temperature. Next, silicidation was carried out by the RTA at 500°C/1 min in N2 followed by the selective etching. From the J-V characteristics of fabricated Schottky diode, Schottky barrier height (SBH) for electron was reduced from 0.73 eV of Pd2Si to 0.4 eV of PdYb-silicide in case the Pd/Yb thicknesses were 14/6 nm, respectively.

We have developed separation by bonding Si islands (SBSI) process for advanced CMOS LSI applications. In this process, the Si islands that become the SOI regions are formed by selective etching of the SiGe layer in the Si/SiGe stacked layers, and those are bonded to the Si substrate with the thermal oxide layers by furnace annealing. The etching selectivity for SiGe/Si and surface roughness after the SiGe etching were found to be improved by decreasing the HNO3 concentration in the etching solution. The thicknesses of the fabricated Si island and the buried oxide layer also became uniform by decreasing the HNO3 concentration. In addition, it was found that the space formed by SiGe etching in the Si/SiGe stacked layers was able to be filled with the thermal oxide layer without furnace annealing.